TITLE

Low-temperature atomic-layer-deposition lift-off method for microelectronic and nanoelectronic applications

AUTHOR(S)
Biercuk, M. J.; Monsma, D. J.; Marcus, C. M.; Becker, J. S.; Gordon, R. G.
PUB. DATE
September 2003
SOURCE
Applied Physics Letters;9/22/2003, Vol. 83 Issue 12, p2405
SOURCE TYPE
Academic Journal
DOC. TYPE
Article
ABSTRACT
We report a method for depositing patterned dielectric layers with submicron features using atomic layer deposition. The patterned films are superior to sputtered or evaporated films in continuity, smoothness, conformality, and minimum feature size. Films were deposited at 100–150 °C using several different precursors and patterned using either electron-beam or photoresist. The low deposition temperature permits uniform film growth without significant outgassing or hardbaking of resist layers. A lift-off technique presented here gives sharp step edges with edge roughness as low as ∼10 nm. We also measure dielectric constants (κ) and breakdown fields for the high-κ materials aluminum oxide (κ∼8–9), hafnium oxide (κ∼16–19), and zirconium oxide (κ∼20–29), grown under similar low temperature conditions. © 2003 American Institute of Physics.
ACCESSION #
10848398

 

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