TITLE

Fabrication of 60-nm transistors on 4-in. wafer using nanoimprint at all lithography levels

AUTHOR(S)
Wei Zhang; Chou, Stephen Y.
PUB. DATE
August 2003
SOURCE
Applied Physics Letters;8/25/2003, Vol. 83 Issue 8, p1632
SOURCE TYPE
Academic Journal
DOC. TYPE
Article
ABSTRACT
Nanoimprint lithography (NIL) is a paradigm-shift method that has shown sub-10-nm resolution, high throughput, and low cost. To make NIL a next-generation lithography tool to replace conventional lithography, one must demonstrate the needed overlay accuracy in multilayer NIL, large-area uniformity, and low defect density. Here, we present the fabrication of 60-nm channel metal–oxide–semiconductor field-effect transistors on whole 4-in. wafers using NIL at all lithography levels. The nanotransistors exhibit excellent operational characteristics across the wafer. The statistics from consecutive multiwafer processing show an average overlay accuracy of 500 nm over the entire 4-in. wafer. The accuracy is much better when the field size is reduced. The overlay accuracies are limited by the current alignment method and can be improved substantially. The work presents a significant advance in nanoimprint development and its applications in manufacturing of integrated electrical, optical, chemical, and biological nanocircuits. © 2003 American Institute of Physics.
ACCESSION #
10603814

 

Related Articles

  • N-channel Junction-less Vertical Slit Field-Effect Transistor (VeSFET): Fabrication-based Feasibility Assessment. Zhixian Chen; Kamath, Aashit; Singh, Navab; Nansheng Shen; Xiang Li; Guo-Qiang Lo; Dim-Lee Kwong; Kasprowicz, Dominik; Pfitzner, Andrzej; Maly, Wojciech // International Proceedings of Computer Science & Information Tech;2012, Vol. 32, p96 

    The silicon implementation of junction-less Vertical Slit Field-Effect Transistor (VeSFET) fabricated on SOI wafer using conventional CMOS processes is presented. The twin poly-Si gates on the side walls of the vertical slit are defined using damascene process making them self-aligned and free...

  • Semiconductor wafer annealing meets the 28 nm node. Hebb, Jeff // Laser Focus World;Jun2011, Vol. 47 Issue 6, p49 

    The article reports on the advancement in thermal processing equipment for semiconductor wafer manufacturing that can be accomplished by laser spike annealing (LSA) or flash lamp annealing (FLA). Thermal processing is significant in the formation of complementary metal-oxide semiconductor (CMOS)...

  • The Low-frequency Noise of Strained Silicon n-MOSFETs. Simoen, E.; Eneman, G.; Verheyen, P.; Delhougne, R.; Rooyackers, R.; Loo, R.; Vandervorst, W.; De Meyer, K.; Claeys, C. // AIP Conference Proceedings;2005, Vol. 780 Issue 1, p187 

    The low-frequency (LF) noise behavior of n-MOSFETs fabricated on strained silicon (SSi) substrates is described and compared with the results obtained on devices in standard silicon wafers. It is demonstrated that a significant lowering (up to a factor 3) of the 1/f noise can be achieved. This...

  • POWER MOSFETs CONTINUE TO EVOLVE, THANKS TO WAFER THINKING AND INNOVATIVE PACKAGING. Conner, Margery // EDN;2/2/2012, Vol. 57 Issue 3, p24 

    The article reports that innovations in manufacturing processes and packaging have helped improve the performance of power metal oxide semiconductor field-effect transistors (MOSFET). Three factors are believed to enable the increase in MOSFETs' power density and these are silicon structures,...

  • Impact of the channel direction on the 1/f noise in SOI-MOSFETs fabricated on (100) and (110) silicon oriented wafers. Gaubert, P.; Cheng, W.; Teramoto, A.; Ohmi, T. // AIP Conference Proceedings;2007, Vol. 922 Issue 1, p43 

    In this paper we present the study of 1/f noise in SOI n- and p-MOSFET fabricated on Si(100) and Si(110) oriented wafers. A comparison of noise performances are first presented, then the impact of the in-plane channel direction on the low frequency noise for each device is investigated. A...

  • Infineon uses carbon nanotubes to send Mosfet structure into power. Bush, Steve // Electronics Weekly;3/3/2004, Issue 2136, p7 

    The article provides information on a Mosfet structure developed by Infineon Technologies. Researchers at Infineon Technologies have used carbon nanotubes to make a Mosfet structure suitable for power applications. The device was made on a metal wafer topped with a thin aluminium oxide...

  • Double-polysilicon self-aligned lateral bipolar transistors. Pengpad, P.; Bagnall, D. M. // Journal of Materials Science: Materials in Electronics;Feb2008, Vol. 19 Issue 2, p183 

    A new lateral bipolar junction transistor that utilises a double-polysilicon self-aligned structure to maximise high-frequency performance is introduced. Silicon-on-oxide (SOI) wafers are used to isolate devices from the substrate and to minimise parasitic substrate capacitances (CJCS0) around...

  • On the beneficial impact of tensile-strained silicon substrates on the low-frequency noise of n-channel metal-oxide-semiconductor transistors. Simoen, E.; Eneman, G.; Verheyen, P.; Delhougne, R.; Loo, R.; Meyer, K. De; Claeys, C. // Applied Physics Letters;5/30/2005, Vol. 86 Issue 22, p223509 

    The low-frequency noise in n-channel metal-oxide-semiconductor field-effect transistors, fabricated on strained silicon (SSi) substrates has been investigated and compared with the results obtained on silicon reference wafers. The strained silicon was deposited on a thin strain-relaxed SiGe...

  • NEMOTEK SELECTS EV GROUP WAFER BONDING/LITHOGRAPHY.  // Electro Manufacturing;May2010, Vol. 23 Issue 5, p4 

    The article reports on the decision of Nemotek Technologies to place repeat order of EV Group Inc.'s wafer bonding and ultraviolet (UV) nonimprint lithography (UN-NIL) systems. It mentions that the systems will be used by Nemotek to address its production demands for wafer-level optics and...

Share

Read the Article

Courtesy of VIRGINIA BEACH PUBLIC LIBRARY AND SYSTEM

Sorry, but this item is not currently available from your library.

Try another library?
Sign out of this library

Other Topics