TITLE

TOOL IMPROVES DESIGN TIMING

AUTHOR(S)
Moretti, Gabe
PUB. DATE
June 2003
SOURCE
EDN;6/26/2003, Vol. 48 Issue 14, p18
SOURCE TYPE
Trade Publication
DOC. TYPE
Article
ABSTRACT
Zenasis Technologies has introduced ZenTime, a tool that uses a hybrid-optimization technology to improve design timing. The tool uses placement-accurate timing to identify timing roadblocks, transistor-level optimization to break the roadblocks by crafting context-specific cells for the critical logic, and physical optimization to restructure surrounding logic. The technique improves timing without introducing power, area, or signal-integrity penalties. The crafted cells that it inserts use the same cell-layout architecture as the standard cell library, so placement-and-routing tools see no difference between the standard cells and the newly crafted cells.
ACCESSION #
10116027

 

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